An information processing apparatus with a plurality of processors being operated in parallel attains the more improved processing efficiency than that with a single processor being operated. In information processing apparatuses of this type, the reproducibility of a program is secured by recording a history of the plurality of processors that have accessed a shared memory, and causing each processor to wait to access the shared memory in accordance with the history when the program is re-executed (for example, see Japanese Laid-open Patent Publication No. 07-13805). Moreover, the reproducibility of a program is secured by recording the order of a plurality of processors that have accessed a shared memory, and permitting the processors to access the shared memory in accordance with the order when the program is re-executed (for example, see Japanese Laid-open Patent Publication No. 07-13943).
In a case where instruction processing and data transfer processing that is executed asynchronous to the instruction processing are executed in parallel with each other, the reproducibility of a program is secured by dividing a transfer period of the data into a predetermined number of terms, and synchronizing the instruction processing with the data transfer processing for each term (for example, see Japanese Laid-open Patent Publication No. 2007-334392). Moreover, in a simulator that simulates executions of a synchronous instruction and an asynchronous instruction, the reproducibility of the execution of the asynchronous instruction is secured by executing data transfer based on the asynchronous instruction during a period when a predetermined number of synchronous instructions, which is a condition set in advance, are executed (for example, see Japanese Laid-open Patent Publication No. 04-277840).